1. Field of the Invention
This invention pertains to the field of semiconductor integrated circuit (IC) fabrication, and in particular, to the field of semiconductor IC fabrication involving bipolar-complementary metal-oxide-semiconductor (BiCMOS) circuits.
2. Description of Related Art
As is well known in the art, CMOS transistors, including both PMOS (p-channel metal-oxide-semiconductor) and NMOS (n-channel metal-oxide-semiconductor) transistors, and bipolar transistors are fabricated on the same substrate in a BiCMOS process. Discussions of the BiCMOS technology and device characteristics may be found in (i) an article entitled "Advanced BiCMOS Technology for High Speed VLSI" by T. Ikeda et al., IEDM technical digest, International Electron Devices Meeting, Los Angeles, Dec. 7-10, 1986, pp. 408-411, and (ii) an article entitled "A Production Proven High Performance 1.0 .mu.m Double-level Polysilicon BiCMOS Technology" by P. Tong et al., Semiconductor Technical Journal, vol. 5, No. 1, 1990, pp. 106-112.
A process for fabricating BiCMOS integrated circuits is shown in FIG. 1.
FIG. 1a shows a semiconductor structure being fabricated in a BiCMOS process, at the step after a pattern of the photoresist layer 103 is developed in preparation for etching the immediately underlying polycide layer 104. The polycide layer 104 can be, for example, a tungsten silicide/polysilicon stack. The structure carved out of the polycide layer 104 by the etching step forms the gate of an NMOS transistor. As shown in FIG. 1a, the regions 100 and 101 are, respectively, regions in which a bipolar transistor and a NMOS transistor are to be fabricated. Region 100 includes an n-type buried layer 108 underneath an N-well 110, which included a collector plug region 109. Region 101 includes a p-type buried layer 107 beneath a P-well 106.
On the wafer surface, on top of both P-well 106 and N-Well 110, is shown an oxide layer, which includes gate oxide 105a and field oxide 105b regions. A polycide layer 104 is formed on top of the oxide layers 105a and 105b. In the process shown, the polycide layer 104 comprises tungsten silicide on top of a phosphorus-doped polysilicon.
FIG. 1b shows the semiconductor structure after a selective etch of polycide layer 104 to form the gate of the NMOS transistor, and removal of photoresist layer 103. An annealing step for the polycide gate 104 is then performed, which is followed by the deposition of a layer 111 of low temperature oxide (FIG. 1c). This low temperature oxide layer 111 is then anisotropically etched to leave portions 111a and 111b (FIG. 1d), called oxide spacers, on the sidewalls of the polycide gate 104. Generally, the oxide layer 111 is overetched in forming spacers 111a and 111b, in order to achieve across the wafer uniform junction depth and sheet resistivity at the MOS transistors' source and drain regions. Uniformity in these regions is important because the implant range of the dopant species, such as arsenic or boron difluoride, is sensitive to the oxide thickness left on top of the active regions after the spacer etch. A uniform junction depth and sheet resistivity is necessary to manufacture devices which actual electrical characteristics are closer to the predicted values used in their design.
Photoresist layer 112 is then applied and patterned for implanting p-type ionic species in the bipolar region 100 to form the base 113 of a bipolar transistor (FIG. 1e). During this step, an ionic species such as boron is implanted into the bare silicon surface exposed after the spacer etch. This implant step may cause "channeling", if no special precaution is taken. Channeling occurs when atoms of an implanted species are introduced into the crystal lattice at such an angle that they are met with little resistance in the interatomic space until they reach a great depth. This effect causes a small but significant impurity concentration deep into the implanted surface called the "channeling tail." The channeling tail is a major obstacle to achieving small base width desirable in advanced bipolar devices.
One method to alleviate the channeling effect is to implant the ionic species at an angle to the lattice structure, such as 7 degrees from the normal of the surface of implant. Such off-axis implants, however, cause other device performance problems because of the non-uniform concentration over the surface due to "shadows" cast by other structures on the semiconductor surface, affecting adversely device characteristics to cause such effects as perimeter-punch through and tunnelling leakage currents. Examples of effects can be found in "Effect of off-axis Implant on the characteristics of Advanced Self-aligned Bipolar Transistors," by C.T. Chuang et al., IEEE Electron Device Letters, Vol. EDL-8, No. 7, July, 1987, pp. 321-23.
After the base implant step, and having stripped off photoresist 112, a new photoresist layer 114 is deposited and patterned to open the collector contact 114c inside the collector plug region 109 of the bipolar transistor in bipolar region 100. The source 114a and drain 114b regions of the NMOS transistor in region 101 are also exposed at this step. The exposed regions are then implanted with n-type ionic species (FIG. 1f). After an oxygen plasma cleaning step (commonly known as ashing) is applied to remove photoresist 114, the base contact areas 116a and 116b of the bipolar transistor, and the source and drain regions of the PMOS transistor (not shown) are formed by suitably patterning on the photoresist layer 115 and implanting with p-type ionic species (FIG. 1g).
After stripping off photoresist layer 115, a blanket layer of low temperature oxide 117b is deposited over the entire surface, including the electronic-states rich bare silicon base region 113. This low temperature oxide layer is then patterned and selectively etched to form a contact region for use with a second film of polysilicon (see below), e.g. the emitter contact 117a shown.
A second polysilicon film ("POLY II") is then deposited. Thereafter, a layer of photoresist is deposited over this POLY II layer, and is suitably patterned in accordance with a POLY II mask and etched to define second polysilicon features, including the emitter of the Bipolar transistor 117 in bipolar region 100. The remaining portions of the POLY II layer are overlaid by a layer of photoresist which is suitably patterned and developed in accordance with a POLY II implant mask to expose conductive sections for ion implant. Such regions for ion implant include prospective emitter regions in the remaining portions of the POLY II layer. A POLY II implant is then made using an n-type dopant.
The photoresist layer which defines the exposed POLY II features is then removed. The implanted n-type dopant in the POLY II features is driven into the base region 113 through the emitter contact 117a by an oxidation cycle. The surface of the wafer is then provided with a layer of undoped oxide, followed by and a layer of Boro-Phospho-Silicate glass (BPSG) 119, which is patterned and selectively etched to allow the circuit elements to be interconnected by one or more layers of metallization 118 insulated by intermetal dielectric layer 120. The entire surface is then passivated by a passivation layer 121. The completed semiconductor structure is shown in FIG. 1h.
In the BiCMOS process just described, the finished bipolar transistors are prone to excessive emitter-base junction recombination currents. Such currents are observed in a special case study "Increased Current Gain and Suppression of Peripheral Base Currents in Silicided Self-Aligned Narrow-Width Polysilicon-Emitter Transistors of an Advanced BiCMOS Technology" IEEE Electron Device Letters, vol. EDL-9, No. 5, pp. 247-49, May 1988, by M.H. El-Diwany et al., in a different context.
To prevent damage to the bipolar active region, the oxide spacer etching step has been designed to leave a suitable thickness (e.g. 150 angstroms) of oxide on top of the active regions. However, this approach causes undesirable varying CMOS device performance because of (1) the inherent variations in thickness of the oxide layer 111 (which forms the oxide spacers 111a and 111b), and (ii) the selectivity of the etch and the non-uniformity caused by the oxide etcher. The major contribution is observed to stem from the configuration of the oxide etcher, which etches at different rates at the center of the wafer and at the edge of the wafer. Typically, across the wafer, variations of up to 350 .ANG. can result.